1. Field of the Invention
The present invention relates to a pipeline A/D converter, and more particularly to a technique for correcting an output thereof.
2. Description of Related Art
Following digitization in the fields of audiovisual, information communications, and the like, faster speeds and higher resolution are required in AD converters, which are key devices. Pipeline AD converters have been much used in recent years as excellent circuits in terms of speed and power consumption. However, with the increasing performance of devices, greater accuracy is sought in pipeline AD converters, together with high speed, low voltage, multi-bit conversion and low cost.
FIG. 16 is a block diagram showing the basic configuration of a pipeline A/D converter. This pipeline A/D converter includes n stages, that is, a first stage 1[1] to an nth stage 1[n], that are connected in cascade, and a flash AD converter 2 as a final stage. An input analog signal Vin is converted to a digital signal one bit at a time from a most significant bit to a least significant bit by the n stages. An output signal resulting from the input analog signal elm being A/D converted with a desired number of bits is obtained as a result of output digital signals of the n stages and the flash AD converter 2 being combined by a digital operation portion 6.
While only the configuration of the first stage 1[1] is shown in detail in FIG. 16, the configuration of the other stages is similar. That is, each stage is constituted by an AD conversion portion 3, a DA conversion portion 4, and a remainder operation portion 5.
The AD conversion portion 3 generates and outputs a digital signal obtained by ternarizing an analog signal input to the stage, and also supplies the digital signal to the DA conversion portion 4. The DA conversion portion 4 generates an analog reference signal based on the digital signal output by the AD conversion portion 3, and supplies the analog reference signal to the remainder operation portion 5. The remainder operation portion 5 generates a remainder analog signal by subtracting the analog reference signal output by the DA conversion portion 4 and performing amplification, with respect to the input analog signal of the stage, and supplies the remainder analog signal to the next stage as an input analog signal.
FIG. 17 shows a circuit for obtaining a prescribed function using the DA conversion portion 4 and the remainder operation portion 5. The DA conversion portion 4 is composed of a logical operation portion 7 and a voltage supply portion 8. The other elements, that is, an operational amplifier 9, a sampling capacitor Cs, a feedback loop capacitor Cf, and switches 10 to 12 constitute the remainder operation portion 5 in FIG. 16. The analog reference signal output by the DA conversion portion 4 is supplied to a connection node between the sampling capacitor Cs and the switch 10. Also, the operational amplifier 9 side of the sampling capacitor Cs is connected to a bias0 via a switch 15. Note that in the following description, the capacitance values of the sampling capacitor Cs and the feedback loop capacitor Cf respectively will be represented by Cs and Cf.
The voltage supply portion 8 selects and supplies ternary reference voltages +Vref, 0V and −Vref by switching three switches. The logical operation portion 7 outputs a signal for switching the switches of the voltage supply portion 8, based on a value of the digital signal output from the AD conversion portion 3. In the voltage supply portion 8, one of the ternary reference voltages is selected according to the value of the digital signal, and supplied as an analog reference signal Vdac.
This circuit performs operations of a sampling period and an amplifying period, as a result of a clock φ1 and a clock φ2 shown in FIG. 17 alternately taking high level (H) and low level (L) values. In a state where the clock φ1 is H and the clock φ2 is L, the switches 10 and 11 are on and the switch 12 is off, resulting in the input analog signal Vin being sampled in the sampling capacitor Cs. In a state where the clock φ1 is L and the clock φ2 is H, the switches 10 and 11 will be off and the switch 12 will be on, resulting in the charge sampled in the sampling capacitor Cs being redistributed to the sampling capacitor Cs and the feedback loop capacitor Cf. Also, the logical operation portion 7 operates and the analog reference signal Vdac is supplied from the voltage supply portion 8 to the sampling capacitor Cs. As a result, an output signal Vout amplified by the operational amplifier 9 will be as follows:Vout={(Cs+Cf)/Cf}·Vin−(Cs/Cf)·Vdac  (1)
If Cs=Cf is set, then:Vout=2·Vin−Vdac  (2)
This output signal Vout of the operational amplifier 9 will be described in more detail with reference to the input-output characteristics of FIG. 18. The horizontal axis in FIG. 18 shows the input analog signal Vin supplied to each stage. The vertical axis shows the output signal Vout of the operational amplifier 9. As shown in this figure, the level of the input analog signal Vin on the horizontal axis is sectioned into a first range (−Vref to −Vref/4), a second range (−Vref/4 to +Vref/4), and a third range (+Vref/4 to +Vref).
The AD conversion portion 3 generates a ternary digital signal from the input analog signal Vin, using a reference voltage corresponding to the boundary of each range. In the voltage supply portion 8, one of the voltages +Vref, 0V and −Vref is selected, using a control signal output by the logical operation portion 7 based on this digital signal. Further, as a result of the operation of the equation (2), the input-output characteristics of the output signal Vout of the operational amplifier 9 relative to the input analog signal Vin will be as shown in FIG. 18.
In this way, the output signal Vout of the operational amplifier 9 can be prevented from exceeding the input range of the AD conversion portion 3 of the next stage 1, by generating an analog reference signal according to the level of the input analog signal Vin, and performing addition/subtraction with respect to the input analog signal Vin. Also, when the capacitance values of the sampling capacitor Cs and the feedback loop capacitor Cf are equal, as mentioned above, the analog input-output characteristics of each stage will be ideal. That is, a gain by the operational amplifier 9 will be exactly “2”, and a discontinuous width in a nonlinear portion (portion where Vin=±Vref/4) of the characteristics in FIG. 18 will be a Vref equivalent to exactly one bit.
However, in practice, a slight error exists between the capacitance values of the sampling capacitor Cs and the feedback loop capacitor Cf. An error occurs in the gain caused by this capacitance value error, and the analog input-output characteristics of the stage end up differing from the prescribed characteristics. That is, when Cf<Cs, the discontinuous width will be greater than one bit, and when Cf>Cs, the discontinuous width will be less than one bit.
The above capacitance value error is the main cause of a degradation in analog input-output characteristics of a stage, and eliminating this error will lead to improvement in the conversion accuracy of a pipeline A/D converter. However, in the case where the resolution of the pipeline A/D converter is 12 bits or more, the tolerable error will be no more than around 0.04%. Correcting this error in the analog signal region is extremely difficult, and so requires error correction using digital processing.
A pipeline A/D converter such as shown in FIG. 19 is disclosed in JP 2006-67201A, as an example of a configuration for performing correction of conversion errors caused by such capacitance value errors. This A/D converter includes a plurality of stages 30 and variable stages 30A, a digital calculation portion 31, a control portion 32, a plurality of input switching portions 33, a stage evaluation portion 34, a plurality of correction value computing portions 35, and an output correction portion 36. The stages 30 and the variable stages 30A have similar functions to the above-mentioned stages. The digital calculation portion 31 is provided with digital calculation cores 31a that correspond with the stages and add the digital output of the corresponding stage to the result of shifting the digital output from the previous stage by 1 bit.
The control portion 32 controls operation of the group of switches in each input switching portion 33 and each variable stage 30A. The input switching portions 33 are provided in correspondence with the variable stages 30A, and switch the input of the corresponding variable stages 30A between a normal input signal and a test signal, under the control of the control portion 32. The normal input signal refers to an analog signal input to each stage when performing a normal conversion operation. The test signal is an analog signal of a prescribed size for detecting capacitance value errors in a stage. The test signal is, for example, generated using a D/A converter or the like (not shown).
The stage evaluation portion 34 estimates an analog output error of each variable stage 30A, based on the digital output of the output correction portion 36. That is, in a state where a test signal has been input to a variable stage 30A (test stage) whose capacitance value error is to be estimated, a conversion error of a size that depends on the capacitance value error of the test stage is included in the digital output obtained from the pipeline A/D converter. Accordingly, the analog output error is estimated from this digital output.
The correction value computing portions 35 are provided in correspondence with the variable stages 30A, and generate output error characteristics for the variable stages 30A, based on the capacitance value errors estimated by the stage evaluation portion 34. Based on these characteristics, the correction value computing portions 35 compute digital output errors for the corresponding variable stages 30A as digital correction values, using intermediate outputs of the digital calculation portion 31 input via delay elements 37.
The output correction portion 36 corrects the digital outputs of the digital calculation portion 31, based on the digital correction values output from the correction value computing portions 35.
In this way, with regard to each variable stage 30A, an output error caused by the capacitance value error between the feedback loop capacitor and the sampling capacitor in the variable stage 30A is estimated, and a digital correction value is computed based on this estimated error. The digital output of the pipeline A/D converter is then corrected using these digital correction values.
Also, in JP 2007-13885A, a specific configuration for supplying a test signal such as mentioned above is disclosed.